Method and circuit for acquisition

ABSTRACT

Frame synchronization is quickly established to acquire an RF channel in a short time. Numerically controlled oscillators  1 - 1  to  1 - 3 , complex calculation circuits  2 - 1  to  2 - 3 , band limit filters  3 - 1  to  3 - 3 , a selector  7 , a phase error detection circuit  9 , a loop filter  10 , and an AFC circuit  11  compose a carrier regeneration loop for removing the frequency error of the carrier included in an in-phase component I and a quadrant component Q of the baseband signal input to the complex calculation circuits  2 - 1  to  2 - 3 . A timing generator  6  detects which of frame synchronization pattern detection circuits  5 - 1  to  5 - 3  has detected a frame synchronization pattern, provides the selector  7  with a selection signal corresponding to the decision result, and sends a switch signal to the AFC circuit  11 . Thereafter, the carrier for removing the frequency error included in the baseband signal is regenerated to acquire an RF channel in a short time.

FIELD OF THE INVENTION

The present invention relates to a synchronization acquiring circuit foracquiring an RF channel, and more particularly to a synchronizationacquiring circuit capable of acquiring an RF channel in a short time.

RELATED ART

In receiving digital broadcasting of a broadcasting satellite (BS), asynchronization acquiring circuit such as shown in FIG. 15 is used toestablish a synchronization and acquire a radio frequency (RF) channelof a predetermined frequency.

In BS digital broadcasting, a digital signal is transmitted in the framewhich is time divisionally divided and multiplexed by various digitalmodulation methods. In order to acquire an RF channel, it is necessaryto detect a frame synchronization pattern and establish asynchronization.

The frame synchronization pattern is formed by a digital signal ofsymbols transmitted by a BPSK modulation method. In the synchronizationacquiring circuit shown in FIG. 15, a BPSK demapper 73 recovers thedigital signal and a frame synchronization pattern detection circuit 74detects a predetermined frame synchronization pattern.

The BPSK demapper 73 specifies a signal point position on an I-Q vectorplane in accordance with the in-phase component I and a quadrature-phasecomponent Q of a baseband signal, and specifies the value (0 or 1) ofthe digital signal in accordance with the phase obtained from the signalpoint.

For example, the BPSK demapper 73 specifies the digital signal value as“1” if the signal point is in the hatched line area of an I-Q vectorplane shown in FIG. 16, and as “0” if it is in the white area of the I-Qvector plane. Namely, depending upon whether the signal pointrepresentative of the phase of a received signal is in which one of thetwo areas of the I-Q vector plane divided by a BPSK decision criterionborder line BL, the BPSK demapper 73 specifies the value of thetransmitted digital signal.

In receiving BS digital broadcasting, an outdoor unit (ODU) firstdown-converts a received radio wave into a broadcastingsatellite—intermediate frequency (BS-IF) signal as an intermediatefrequency signal.

This BS-IF signal is quasi-synchronization detected by using a localoscillation signal having a fixed frequency to obtain a baseband signal.

Since the local oscillation signal used for quasi-synchronizationdetection has a fixed frequency, a frequency error generated duringdown-converting by ODU appears in the BS-IF signal and also in thebaseband signal.

In the synchronization acquiring circuit, frequency synchronization forregenerating the carrier is not performed when the frame synchronizationpattern is to be detected.

Therefore, in detecting the frame synchronization pattern, the signalpoint of each symbol on the I-Q vector plane specified by the BPSKdemapper 73 from the baseband signal moves on the I-Q vector plane alongthe rotation direction. Namely, the phase angle of the received signalchanges and a phase rotation occurs.

For example, the position of a signal point assigned a bit “1” on thetransmission side moves on the I-Q vector plane along the rotationdirection as shown in FIG. 17, while symbols of the framesynchronization pattern of 20 bits are received.

In order to correctly detect the frame synchronization pattern from thebaseband signal containing such a frequency error, it is required thatthe signal point assigned a predetermined digital signal value (“0” or“1”) on the transmission side does not ride across the BPSK decisioncriterion border line BL of the I-Q vector plane, while the symbolsconstituting the frame synchronization pattern are received on thereception side.

In the case wherein the signal point assigned a predetermined digitalsignal value (“0” or “1”) on the transmission side rides across the BPSKdecision criterion border line BL of the I-Q vector plane on thereception side, although the BPSK demapper 73 converts the digitalsignal value into an inverted value, the frame synchronization patterncannot be detected correctly.

In the above-described synchronization acquiring circuit, the BPSKdemapper specifies the position of a signal point on the I-Q vectorplane having the fixed BPSK decision criterion border line BL to recoverthe digital signal.

There is known a synchronization acquiring circuit which can use thetransmission method for the BS digital broadcasting and can correctlydetect the frame synchronization pattern even if the baseband signal hasa phase error, by providing a plurality of BPSK demappers havingdifferent positions (rotated phases) of the BPSK judgement criterionborder line BL.

Even with such a synchronization acquiring circuit, each BPSK demappterspecifies the position of a signal point on one I-Q vector plane havinga fixed BPSK judgement criterion border line BL to reproduce the digitalsignal. Therefore, if the frequency error contained in the basebandsignal is larger than a predetermined value, the frame synchronizationpattern cannot be detected correctly.

If the BPSK decision criterion border line BL is fixed, the maximumfrequency error Δf up to which the signal assigned a predetermineddigital signal value (0 or 1) on the transmission side can be receivedwithout riding across the BPSK decision criterion border line BL whilethe reception side receives the symbols representative of the framesynchronization pattern, is obtained by the formula 1:Δf=((π/N)/2π)×Fs  (Formula 1)where is a ratio of the circumference of a circle to its diameter, N isthe number of symbols of a frame synchronization pattern, and Fs is asymbol rate.

For example, the maximum frequency error capable of correctly receivinga frame synchronization pattern having 20 symbols of BS digitalbroadcasting at a symbol rate of 28.860 MHz is ±721.5 kHz.

In the BS digital broadcasting, in order to acquire one RF channel, itis necessary to detect the frame synchronization pattern in the range of±2 MHz of the frequency error contained in the baseband signal.

To this end, in the conventional synchronization acquiring circuit,three types of scanning are required to be sequentially performed byadjusting the output of an AFC circuit 79. The three types of scanningincludes: scanning for the detection of a frame synchronization patternif the frequency error contained in the baseband signal is 0 Hz;scanning for the detection of a frame synchronization pattern if thefrequency error is +1.3 MHz; and scanning for the detection of a framesynchronization pattern if the frequency error is −1.3 MHz.

With the conventional synchronization acquiring circuit, the frequencyerror contained in the baseband signal becomes maximum when a differencebetween the frequency at which an RF channel is acquired and thefrequency of the local oscillator for tuning in at the reception sidebecomes maximum.

In this case, it is necessary to sequentially execute the three types ofscanning so that it takes a long time to acquire an RF channel.

The invention has been made under such a circumstance, and an object ofthe invention is to provide a synchronization acquiring circuit capableof establishing a synchronization and acquiring a channel in a shorttime.

DISCLOSURE OF THE INVENTION

In order to achieve the above object, according to a first aspect of theinvention, there is provided a synchronization acquiring circuit forreceiving a baseband signal transferred as an intermediate frequencysignal obtained by down-converting a received radio wave and foracquiring a radio frequency channel, comprising:

a plurality of pattern detection means disposed in parallel eachperforming an operation of receiving the baseband signal transferred bythe intermediate frequency signal in a different frequency range anddetecting a predetermined frame synchronization pattern; and

carrier recovery means for establishing a frame synchronization andrecovering a carrier to be used for removing a frequency error of thebaseband signal when one of the plurality of pattern detection meansdetects the frame synchronization pattern.

More specifically, the synchronization acquiring circuit comprises:

first pattern detection means for receiving the baseband signaltransferred by the intermediate frequency signal in a predeterminedfrequency range and detecting a predetermined frame synchronizationpattern;

second pattern detection means for receiving the baseband signaltransferred by the intermediate frequency signal in a frequency rangehigher than the frequency range of the intermediate frequency signaltransferring the baseband signal from which the first pattern detectionmeans can detect the frame synchronization pattern, and detecting thepredetermined frame synchronization pattern;

third pattern detection means for receiving the baseband signaltransferred by the intermediate frequency signal in a frequency rangelower than the frequency range of the intermediate frequency signaltransferring the baseband signal from which the first pattern detectionmeans can detect the frame synchronization pattern, and detecting thepredetermined frame synchronization pattern; and

carrier recovery means for establishing a frame synchronization andrecovering a carrier to be used for removing a frequency error of thebaseband signal when one of the first to third pattern detection meansdetects the frame synchronization pattern.

It is desired that each of the first to third pattern detection meanscomprises;

signal conversion means for specifying a phase of the received basebandsignal and converting the phase into a digital signal corresponding tothe specified phase; and

signal decision means for deciding whether the digital signal generatedthrough conversion by the signal conversion means contains thepredetermined frame synchronization pattern.

It is possible to detect a frame synchronization pattern transmitted bythe phase modulation method such as a BPSK modulation method.

It is desired that:

the signal conversion means has:

eight de-mapping means each for specifying the phase of the basebandsignal on a phase plane having a decision criterion border line whosephase is rotated by φ=45°×n (where n is an integer of 0 to 7) andobtaining the converted digital signal, the decision criterion borderline being used for specifying a value of the converted digital signalcorresponding to the specified phase of the baseband signal; and

the signal decision means has:

eight sequence decision means for deciding whether each digital signalsequence generated through conversion by each of the eight de-mappingmeans contains the predetermined frame synchronization pattern; and

means for notifying the carrier recovery means of that the framesynchronization pattern was detected, if at least one of the eightsequence decision means decides that the digital signal sequencecontains the predetermined frame synchronization pattern.

It is possible to correctly detect a frame synchronization pattern evenif a phase error is generated in the baseband signal to be transmittedby the hierarchical transmission method by which data is multiplexed byvarious modulation methods.

It is desired that:

each of the first to third pattern detection means comprises:

waveform data making means for creating waveform data to be used forrotating a phase of the baseband signal; and

complex calculation means for rotating the phase of the baseband signalby executing a complex number calculation between the waveform datacreated by the waveform making means and the received baseband signal;and

the carrier recovery means comprises:

identification means for identifying one of the first to third patterndetection means which detected the frame synchronization pattern;

signal selection means for selecting the baseband signal whose phase wasrotated by the complex calculation means of one of the first to thirdpattern detection means identified by the identification means;

phase error identification means for identifying a phase error bycomparing the phase of the baseband signal selected by the signalselection means and an absolute phase;

frequency error identification means for identifying a frequency errorcontained in the baseband signal in accordance with the phase erroridentified by the phase error identification means; and

carrier recovery means for recovering a carrier to be used for removingthe phase error and frequency error contained in the baseband signal, bycontrolling the waveform data making means of one of the first to thirdpattern detection means identified by the identification means inaccordance with the phase error identified by the phase erroridentification means and the frequency error identified by the frequencyerror identification means.

After the frame synchronization is established, phase and frequencysynchronization can be made for removing the phase and frequency errorscontained in the baseband signal.

According to a second aspect of the present invention, there is provideda synchronization acquiring circuit for receiving a baseband signaltransferred as an intermediate frequency signal obtained throughfrequency conversion of a received radio wave and for acquiring a radiofrequency channel of BS digital broadcasting, wherein:

the baseband signal is received which contains a frequency errorcorresponding to a whole frequency range of the intermediate frequencysignal, the baseband signal being used for acquiring the radio frequencychannel, a frame synchronization pattern is detected through conversioninto a digital signal and in correspondence with the frequency error,and a carrier synchronized with a frequency of the baseband signal isrecovered in accordance with a range of the frequency error contained inthe baseband signal from which the frame synchronization pattern wasdetected, to thereafter establish a frame synchronization.

According to the second aspect, the frame synchronization pattern can bedetected from the digital signal converted in correspondence with therange of a frequency error contained in the baseband signal received foracquiring a radio frequency channel of BS digital broadcasting. It istherefore possible to quickly establish the frame synchronization andacquire an RF channel in a short time.

According to a third aspect of the present invention, there is provideda synchronization acquiring circuit for receiving a baseband signaltransferred as an intermediate frequency signal obtained bydown-converting a received radio wave and for acquiring a radiofrequency channel, comprising:

signal conversion means for identifying a phase of a received basebandsignal phase-modulated in a symbol unit and converting the basebandsignal into a digital signal corresponding to the identified phase;

a plurality of pattern detection means disposed in parallel fordetecting a predetermined frame synchronization pattern transferred bythe baseband signal, in accordance with the digital signal generatedthrough conversion by the signal conversion means, each of the pluralityof pattern detection means being related to a frequency of theintermediate frequency signal in a different frequency range; and

frequency control means for changing the frequency of the basebandsignal by an off-set frequency corresponding to a frequency errorcontained in the baseband signal, when one of the plurality of patterndetection means detects the frame synchronization pattern, and forestablishing a frame synchronization after the signal conversion meansidentifies the phase of the baseband signal.

More specifically, according to the third aspect, the synchronizationacquiring circuit for receiving a baseband signal transferred as anintermediate frequency signal obtained by down-converting a receivedradio wave and for acquiring a radio frequency channel, comprises:

first pattern detection means for detecting a predetermined framesynchronization pattern transferred by the baseband signal, inaccordance with the digital signal generated through conversion by thesignal conversion means, if a center frequency of a range assigned tothe radio frequency channel corresponds to a frequency of theintermediate frequency signal in a predetermined frequency range;

second pattern detection means for detecting the predetermined framesynchronization pattern transferred by the baseband signal, inaccordance with the digital signal generated through conversion by thesignal conversion means, if the center frequency of the range assignedto the radio frequency channel corresponds to the frequency of theintermediate frequency signal in a frequency range higher than thefrequency range of the intermediate frequency signal from which thefirst pattern detection means can detect the frame synchronizationpattern;

third pattern detection means for detecting the predetermined framesynchronization pattern transferred by the baseband signal, inaccordance with the digital signal generated through conversion by thesignal conversion means, if the center frequency of the range assignedto the radio frequency channel corresponds to the frequency of theintermediate frequency signal in a frequency range higher than thefrequency range of the intermediate frequency signal from which thesecond pattern detection means can detect the frame synchronizationpattern;

fourth pattern detection means for detecting the predetermined framesynchronization pattern transferred by the baseband signal, inaccordance with the digital signal generated through conversion by thesignal conversion means, if the center frequency of the range assignedto the radio frequency channel corresponds to the frequency of theintermediate frequency signal in a frequency range lower than thefrequency range of the intermediate frequency signal from which thefirst pattern detection means can detect the frame synchronizationpattern; fifth pattern detection means for detecting the predeterminedframe synchronization pattern transferred by the baseband signal, inaccordance with the digital signal generated through conversion by thesignal conversion means, if the center frequency of the range assignedto the radio frequency channel corresponds to the frequency of theintermediate frequency signal in a frequency range lower than thefrequency range of the intermediate frequency signal from which thefirst fourth detection means can detect the frame synchronizationpattern; and

frequency control means for transforming the frequency of the basebandsignal by an off-set frequency corresponding to a frequency errorcontained in the baseband signal, when one of the first to fifth patterndetection means detects the frame synchronization pattern, for makingthe signal conversion means identify a phase of the baseband signal, andfor making the first pattern detection means detect the framesynchronization pattern to thereafter establish a frame synchronization.

According to the third aspect, the first to fifth pattern detectionmeans can detect the frame synchronization pattern in accordance withthe digital signal generated through conversion by the signal conversionmeans, if the center frequency of the band assigned to the radiofrequency channel corresponds to the frequency of the intermediatefrequency signal in the predetermined frequency range.

As the frame synchronization pattern is detected, the frequency of thebaseband signal is changed by using the off-set frequency correspondingto the frequency error contained in the baseband signal, and the firstpattern detection means detects the frame synchronization pattern.

If the first pattern detection means is set so that it can detect theframe synchronization pattern from the baseband signal having a broaderband than other pattern detection means, the broader frequency range canbe scanned quickly and the stable frame synchronization can beestablished.

It is desired that:

the signal conversion means has:

eight de-mapping means each for specifying the phase of the basebandsignal on a phase plane having a decision criterion border line whosephase is rotated by φ=45°×n (where n is an integer of 0 to 7) andobtaining the converted digital signal, the decision criterion borderline being used for specifying a value of the converted digital signalcorresponding to the specified phase of the baseband signal;

the first pattern detection means has:

eight sequence decision means each for deciding whether each digitalsignal sequence generated through conversion by each of the eightde-mapping means contains the predetermined frame synchronizationpattern; and

means for notifying the frequency control means of that the framesynchronization pattern was detected, if at least one of the eightsequence decision means decides that the frame synchronization patternis contained;

the second and fourth pattern detection means have each:

eight first rotation sequence decision means for deciding whether thepredetermined frame synchronization pattern is contained, by using threeof eight digital sequences generated trough conversion by the eightde-mapping means; and

the third and fifth pattern detection means have each:

eight second rotation sequence decision means for deciding whether thepredetermined frame synchronization pattern is contained, by using fourof eight digital sequences generated through conversion by the eightde-mapping means.

It is desired that:

first and second rotation sequence decision means each have:

delay means for delaying each bit of the digital signal sequence; and

means for deciding whether the predetermined frame synchronizationpattern is contained, by deriving the digital signal sequence from thedelay means in a manner that the phase of the decision criterion borderline rotates in the same direction as a signal reception time lapses.

The second to fifth pattern detection means can detect a framesynchronization pattern transferred by the baseband signal correspondingto each of different frequency ranges.

More specifically:

the first rotation sequence decision means of the second patterndetection means and the first rotation sequence decision means of thefourth pattern detection means derive the digital signal sequence fromthe delay means in a manner that the phase of the decision criterionborder lines rotate in opposite directions as a signal reception timelapses; and

the second rotation sequence decision means of the third patterndetection means and the second rotation sequence decision means of thefifth pattern detection means derive the digital signal sequence fromthe delay means in a manner that the phase of the decision criterionborder lines rotate in opposite directions as a signal reception timelapses.

It is desired that the frequency control means comprises:

waveform data making means for creating waveform data to be used forrotating a phase of the baseband signal;

complex calculation means for rotating the phase of the baseband signalby executing a complex number calculation between the waveform datacreated by the waveform making means and the received baseband signal;

phase error identification means for identifying a phase error bycomparing the phase of the baseband signal rotated by the complexcalculation means and an absolute phase;

frequency error identification means for identifying a frequency errorcontained in the baseband signal in accordance with the phase erroridentified by the phase error identification means; and

carrier recovery means for recovering a carrier to be used for removingthe phase error and frequency error contained in the baseband signal, bycontrolling the waveform data making means in accordance with the phaseerror identified by the phase error identification means and thefrequency error identified by the frequency error identification means.

According to a fourth aspect of the invention, there is provided asynchronization acquiring method of receiving a baseband signaltransferred as an intermediate frequency signal obtained bydown-converting a received radio wave and for acquiring a radiofrequency channel, comprising:

a first pattern detection step of receiving the baseband signaltransferred by the intermediate frequency signal in a predeterminedfrequency range and detecting a predetermined frame synchronizationpattern;

a second pattern detection step of receiving, at the same time as thefirst pattern detection step, the baseband signal transferred by theintermediate frequency signal in a frequency range higher than thefrequency range of the intermediate frequency signal transferring thebaseband signal from which the first pattern detection step can detectthe frame synchronization pattern, and detecting the predetermined framesynchronization pattern;

a third detection step of receiving, at the same time as the first andsecond pattern detection steps, the baseband signal transferred by theintermediate frequency signal in a frequency range lower than thefrequency range of the intermediate frequency signal transferring thebaseband signal from which the first pattern detection step can detectthe frame synchronization pattern, and detecting the predetermined framesynchronization pattern; and

a carrier recovery step of establishing a frame synchronization andrecovering a carrier to be used for removing a frequency error of thebaseband signal when one of the first to third pattern detection stepsdetects the frame synchronization pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an example of a frame structure used by ahierarchical transmission method.

FIG. 2 is a schematic diagram illustrating mapping of each modulationmethod on the transmission side.

FIG. 3 is a diagram showing the structure of a synchronization acquiringcircuit according to a first embodiment of the invention.

FIG. 4 is a diagram showing an I-Q vector plane used when BPSK demappersrecover a digital signal.

FIG. 5 is a diagram showing the structure of BPSK demappers.

FIG. 6 is a diagram showing the structure of a frame synchronizationpattern detection circuit.

FIG. 7 is a diagram showing the structure of a synchronization detector.

FIG. 8 is a diagram showing the structure of a synchronization acquiringcircuit according to a second embodiment of the invention.

FIG. 9 is a diagram showing the structure of a frame synchronizationpattern detection circuit.

FIG. 10 is a diagram illustrating the positions of signal points bywhich the synchronization acquiring circuit detects a framesynchronization pattern.

FIG. 11 is a diagram showing a synchronization detector.

FIG. 12 is a diagram showing the structure of a frame synchronizationpattern detection circuit.

FIG. 13 is a diagram showing the positions of signal points by which thesynchronization detector detects a frame synchronization pattern.

FIG. 14 is a diagram showing the structure of the synchronizationdetector.

FIG. 15 is a diagram showing the structure of a conventionalsynchronization acquiring circuit.

FIG. 16 is a diagram showing an I-Q vector plane used by a BPSKdemapper.

FIG. 17 is a diagram illustrating a motion of signal points to be causedby a frequency error.

EMBODIMENTS OF THE INVENTION First Embodiment

A synchronization acquiring circuit according to the first embodiment ofthe invention will be described in detail with reference to theaccompanying drawings.

In this synchronization acquiring circuit, an outdoor unit (ODU) or thelike down-converts a received radio wave to obtain a broadcastingsatellite-intermediate frequency (BS-IF) signal which isquasi-synchronization detected by a quadrature detector to obtain abaseband signal. The baseband signal is quantized for establishing asynchronization.

A baseband signal input to the synchronization acquiring circuit isrepetitively transmitted one frame after another after being subjectedto a plurality of modulation methods time divisionally used and havingdifferent C/N (carrier-to-noise) values required, such as 8PSK (phaseshift keying) modulation, QPSK (quadrature PSK) modulation and BPSK(binary PSK) modulation. Such a transmission method is called ahierarchical transmission method.

FIG. 1 is a diagram showing the frame structure used by the hierarchicaltransmission method.

As shown in FIG. 1, one frame is constituted of 39,936 symbols includinga header part 100 of 192 symbols and a plurality of pairs of a mainsignal part 101 of 203 symbols and a burst symbol part 102 of 4 symbols.

The header part 100 includes a frame synchronization pattern 110 whichis transmitted by BPSK modulation, transmission and multiplexingconfiguration control (TMCC) data 111 and a super frame identificationpattern 112.

The frame synchronization pattern 110 is used for transmitting a bitstream for establishing a frame synchronization by using predetermined20 bits among 32 bits. The bit stream (S₁₉S₁₈S₁₇ . . . S₁S₀) in theorder of transmission for establishing a frame synchronization is(11101100110100101000).

The TMCC data 111 is transmission multiplex and configuration controldata representative of the multiplexing configuration of the timedivision and multiplexing modulation.

Eight frames constitute one super frame. The super frame identificationpattern 112 is a pattern for identifying the position of each frame inthe super frame.

The main signal part 101 is transmitted by a TC8PSK (Trellis-coded 8PSK)or QPSK modulation method. The burst symbol part 102 is transmitted byBPSK, is a pseudo noise (PN) signal reset at each frame, and isenergy-spread.

On the transmission side, the following mapping is performed for eachmodulation method.

FIG. 2( a) shows the layout of signal points when 8PSK is used as themodulation method.

With the 8PSK modulation method, digital signals of 3 bits (abc: a, b,c=0 or 1) are assigned eight different phases shown in FIG. 2( a) andtransmitted.

Namely, the 8PSK modulation method uses eight combinations of bitsconstituting one symbol, including (000), (001), (010), (011), (100),(101), (110) and (111). These digital signals each constituted of threebits are converted into the signal positions “0” to “7” on the I-Q(in-phase-quadrature) vector plane on the transmission side as shown inFIG. 2( a). This conversion is called 8PSK mapping.

In FIG. 2( a), as one example, the bit train (000) is converted into asignal point position “0”, the bit train (001) is converted into asignal point position “1”, the bit train (101) is converted into asignal point position “2”, the bit train (100) is converted into asignal point position “3”, the bit train (110) is converted into asignal point position “4”, the bit train (111) is converted into asignal point position “5”, the bit train (011) is converted into asignal point position “6”, and the bit train (010) is converted into asignal point position “7”.

FIG. 2( b) shows the layout of signal points when QPSK is used as themodulation method.

With the QPSK modulation method, digital signals of 2 bits (de: d, e=0or 1) are assigned four different phases shown in FIG. 2( b) andtransmitted.

Namely, the QPSK modulation method uses four combinations of bitsconstituting one symbol, including (00), (01), (10) and (11). In FIG. 2(b), as one example, the bit train (00) is converted into the signalpoint position “1”, the bit train (10) is converted into the signalpoint position “3”, the bit train (11) is converted into the signalpoint position “5”, and the bit train (01) is converted into the signalpoint position “7”. This conversion is called QPSK mapping.

In FIG. 2( b), the relation between the signal point position and itsnumber is set to the relation same as the relation between the signalpoint position and its number of 8PSK shown in FIG. 2( a).

Similarly. FIG. 2( c) is a diagram showing the layout of signal pointswhen BPSK is used as the modulation method. With the BPSK modulationmethod, a digital signal of one bit (f:f=0 or 1) is assigned twodifferent phases and transmitted.

In FIG. 2( c), as one example, the bit “0” is converted into the signalpoint position “0” and the bit “1” is converted into the signal pointposition FIG. 3 shows the synchronization acquiring circuit forestablishing a synchronization by receiving a carrier with which thedigital signal is transmitted by the above-described hierarchicaltransmission method.

As shown in FIG. 3, the synchronization acquiring circuit hasnumerically controlled oscillators 1-1 to 1-3, complex calculationcircuits 2-1 to 2-3, band limit filters 3-1 to 3-3, binary phase shiftkeying (BPSK) demappers 4-1 to 4-3, frame synchronization patterndetection circuits 5-1 to 5-3, a timing generator 6, a selector 7, aphase error detection circuit 8, a frequency error calculation circuit9, a loop filter 10, and an automatic frequency control (AFC) circuit11.

The numerically controlled oscillators 1-1 to 1-3 generate sine wavedata sin θ₁ to sin θ₃ and cosine wave data cos θ₁ to cos θ₃,respectively. The numerically controlled oscillators 1-1 to 1-3 generatedigital signals representative of the amplitudes of the sine wave dataor cosine wave data corresponding to the phase signals θ₁ to θ₃ receivedfrom the AFC circuit 11, and send them to the complex calculationcircuits 2-1 to 2-3.

The complex calculation circuits 2-1 to 2-3 are each made of aninverter, a multiplier and the like, and perform calculations forremoving the phase error and frequency error of the quantized basebandsignal.

More specifically, each of the complex calculation circuits 2-1 to 2-3receives the in-phase component I and quadrature component Q of thebaseband signal containing the phase error and frequency error. Thecomplex calculation circuits 2-1 to 2-3 also receive the sine wave datasin θ₁ to sin θ₃ and cosine wave data cos θ₁ to cos θ₃ from thenumerically controlled oscillators 1-1 to 1-3. The complex calculationcircuits 2-1 to 2-3 perform an inversion process and the like for thereceived sine wave data sin θ₁ to sin θ₃ and cosine wave data cos θ₁ tocos θ₃, and multiply them with the in-phase component I and quadraturecomponent Q of the baseband signal to thereby generate I (in-phase)signals RI1 to RI3 and Q (quadrature) signals RQ1 to RQ3.

The complex calculation circuits 2-1 to 2-3 send the generated I signalsRI1 to RI3 and Q signals RQ1 to RQ3 to the band limit filters 3-1 to3-3.

The band limit filters 3-1 to 3-3 are each made of a digital roll-offfilter or the like having the raised cosine characteristics, and limitthe pass bands of the I signals RI1 to RI3 and Q signals RQ1 to RQ3received from the complex calculation circuits 2-1 to 2-3 to therebygenerate data waveforms having no inter-code interference. The bandlimit filters 3-1 to 3-3 send the band-limited I signals DI1 to DI3 andQ signals DQ1 to DQ3 to the BPSK demappers 4-1 to 4-3.

The band limit filters 3-1 to 3-3 also send the band-limited I signalsDI1 to DI3 and Q signals DQ1 to DQ3 to the selector 7.

The BPSK demappers 4-1 to 4-3 recover the digital signals from thesignal point positions of the baseband signal in the manner opposite tothe BPSK mapping on the transmission side, in order to detect the framesynchronization pattern 110 of 20 symbols transmitted through BPSKmodulation.

More specifically, upon reception of the I signals DI1 to DI3 and Qsignals DQ1 to DQ3 from the band limit filters, the BPSK demappers 4-1to 4-3 obtain received signal points on the I-Q vector plane on thereception side such as shown in FIGS. 4( a) to 4(h). The BPSK demappers4-1 to 4-3 convert the baseband signal into the digital signals (0 or 1)corresponding to the received signal point positions on the I-Q vectorplane.

As shown in FIG. 5, each of the BPSK demappers 4-1 to 4-3 has eight BPSKde-mapping circuits 20 to 27.

Each of the BPSK de-mapping circuits 20 to 27 is made of a read onlymemory (ROM) and the like, and converts the received signal point into adigital signal by using one of eight I-Q vector planes having differentphases of BPSK decision criterion border lines BL shown in FIGS. 4( a)to 4(h).

More specifically, each of the BPSK de-mapping circuits 20 to 27specifies a received signal point and converts it into a digital signal,by using the I-Q vector plane whose BPSK decision criterion border lineBL is rotated by an angle corresponding to φ=45°×n (n is an integer from0 to 7) from the I-Q vector plane on the transmission side.

It is assumed in the following that the BPSK de-mapping circuit 20 firstconverts a signal point into a digital signal by using the I-Q vectorplane shown in FIG. 4( a), and sequentially thereafter the BPSKde-mapping circuits 21 to 27 convert a signal point into a digitalsignal by using the I-Q vector planes shown in FIGS. 4( b) to 4(h).

The BPSK de-mapping circuits 20 to 27 send bit streams B0 to B7 of therecovered digital signals to the frame synchronization pattern detectioncircuits 5-1 to 5-3.

The frame synchronization pattern detection circuits 5-1 to 5-3 shown inFIG. 3 detect frame synchronization patterns from the digital signalsrecovered by the BPSK demappers 4-1 to 4-3. The frame synchronizationpattern detection circuits 5-1 to 5-3 correspond to three differentfrequency ranges representative of frequency errors of the basebandsignal. The frame synchronization pattern detection circuits 5-1 to 5-3receive the bit streams B0 to B7 from the BPSK demappers 4-1 to 4-3 anddetect a frame synchronization pattern 110.

Specifically, for example, the frame synchronization pattern detectioncircuit 5-1 corresponds to a frequency range of ±700 kHz of thefrequency error of +1.3 MHz, the frame synchronization pattern detectioncircuit 5-2 corresponds to a frequency range of ±700 kHz of thefrequency error of 0 Hz of the frequency error, and the framesynchronization pattern detection circuit 5-3 corresponds to a frequencyrange of ±700 kHz of the frequency error of −1.3 MHz of the frequencyerror.

Each of the frame synchronization pattern detection circuits 5-1 to 5-3has eight synchronization detection circuits 30 to 37 and an OR gate 38shown in FIG. 6.

The synchronization detection circuits 30 to 37 all have the samestructure having twenty shift registers (delay latches D₀ to D₁₉),inverters IN for the logical inversion of predetermined bits, and an ANDgate A1, as shown in FIG. 7.

The AND gate A1 outputs a high level voltage when the state (D₁₉D₁₈D₁₇ .. . D₁D₀) of the delay latches D₀ to D₁₉ takes (11101100110100101000).This corresponds to the bit stream of the frame synchronization pattern110. When the output of the AND gate A1 take a high potential, it meansthat one of the synchronization decision circuits 30 to 37 detected theframe synchronization pattern.

When one of the synchronization detection circuits 30 to 37 detects theframe synchronization pattern 110, the OR gate 38 notifies thisdetection to the timing generator 6.

The timing generator 6 shown in FIG. 3 establishes a framesynchronization when it is notified from the frame synchronizationpattern detection circuits 5-1 to 5-3 that the frame synchronizationpattern 110 was detected.

In this case, the timing generator 6 decides which one of the framesynchronization pattern detection circuits 5-1 to 5-3 detected the framesynchronization pattern 110, and sends a selection signal correspondingto the decided one of the frame synchronization pattern detectioncircuits 5-1 to 5-3, to the selector 7.

Namely, when the timing generator 6 decides that the framesynchronization pattern detection circuit 5-1 detected the framesynchronization pattern 110, it sends the selector 7 a selection signalto select the I signal DI1 and Q signal DQ1 output from the band limitfilter 3-1. When the timing generator 6 decides that the framesynchronization pattern detection circuit 5-2 detected the framesynchronization pattern 110, it sends the selector 7 a selection signalto select the I signal DI2 and Q signal DQ2 output from the band limitfilter 3-2. When the timing generator 6 decides that the framesynchronization pattern detection circuit 5-3 detected the framesynchronization pattern 110, it sends the selector 7 a selection signalto select the I signal DI3 and Q signal DQ3 output from the band limitfilter 3-2.

After the timing generator 6 establishes the frame synchronization, itderives the TMCC data 111 to identify the frame multiplex configuration,and sends a TMCC section signal to the frequency error calculationcircuit 9 to specify the TMCC section.

The timing generator 6 also sends a switch signal to the AFC circuit 11which makes one of the numerically controlled oscillators 1-1 to 1-3recover a carrier for acquiring the RF channel under the control of thephase signals θ₁ to θ₃.

In response to the selection signal from the timing generator 6, theselector 7 made of a multiplexer and the like selects a pair of the Isignals DI1 to DI3 and Q signals DQ1 to DQ3 output from one of the bandlimit filters 3-1 to 3-3. The selector 7 inputs the selected I signal DIand W signal DQ to the phase error detection circuit 8.

In accordance with the I signal DI and W signal DQ received from theselector 7, the phase error detection circuit 8 specifies the signalpoint position on the I-Q vector plane to obtain a phase error (receivedsignal phase rotation angle) between the phase of the signal pointposition and the absolute phase.

The phase error detection circuit 8 generates a phase error signal PEDcorresponding to the obtained phase error, and sends it to the frequencyerror calculation circuit 9 and loop filter 10.

The frequency error calculation circuit 9 specifies the TMCC sectionfrom the TMCC section signal received from the timing generator 6, andcalculates a difference (error frequency) Δf between a desired frequencyand the frequency of the recovered carrier, in accordance with the phaseerror in the TMCC section represented by the phase error signal PEDreceived from the phase error detection circuit 8.

The frequency error calculation circuit 9 notifies the calculated errorfrequency Δf to the AFC circuit 11.

The loop filter is a low pass filter for smoothing the phase errorsignal PED received from the phase error detection circuit 8, andsupplies the smoothed phase error signal PED to the AFC circuit 11 as aphase adjustment signal LΔf.

The AFC circuit 11 generates phase signals θ₁ to θ₃ corresponding to theerror frequency Δf supplied from the frequency error calculation circuit9 and the phase adjustment signal LΔf supplied from the loop filter 10.

The AFC circuit 11 supplies the generated phase signals θ₁ to θ₃ to thenumerically controlled oscillators 1-1 to 1-3 to make them generate thesine wave data sin θ₁ to sin θ₃ and cosine wave data cos θ₁ to cos θ₃.

If the baseband signal received at the complex calculation circuit 2-1contains a frequency error of +1.3 MHz, the AFC circuit 11 performs acomplex number calculation of the phase signal θ₁ to set it to such avalue that the phase of the signal point assigned a predetermined signal(0 or 1) on the transmission side will not rotate.

If the baseband signal received at the complex calculation circuit 2-2does not contain a frequency error (a frequency error of 0 MHz), the AFCcircuit 11 performs a complex number calculation of the phase signal θ₂to set it to such a value that the phase of the signal point assigned apredetermined signal (0 or 1) on the transmission side will not rotate.

If the baseband signal received at the complex calculation circuit 2-3contains a frequency error of −1.3 MHz, the AFC circuit 11 performs acomplex number calculation of the phase signal θ₃ to set it to such avalue that the phase of the signal point assigned a predetermined signal(0 or 1) on the transmission side will not rotate.

The operation of the synchronization acquiring circuit according to thefirst embodiment of the invention will be described.

This synchronization acquiring circuit can acquire an RF channel of BSdigital broadcasting in a short time, because it has a plurality ofreception series for detecting a frame synchronization pattern, thereception series corresponding in number to a plurality of frequencyranges each being representative of a different frequency errorcontained in the baseband signal.

In the synchronization acquiring circuit of the first embodiment of theinvention, the numerically controlled oscillators 1-1 to 1-3, complexcalculation circuits 2-1 to 2-3, band limit filters 3-1 to 3-3, selector7, phase error detection circuit 8, frequency error calculation circuit9, loop filter 10 and AFC circuit 11 constitute a carrier reproductionloop which removes the frequency error of the carrier contained in thein-phase component I and quadrature component Q of the baseband signalinput to the complex calculation circuits 2-1 to 2-3.

More specifically, first the complex calculation circuits 2-1 to 2-3receive the in-phase component I and quadrature component Q of thebaseband signal which are obtained by detecting the BS-IF signal of thereceived radio wave down-converted by an ODU (not shown), by using alocal oscillation signal generated by a local oscillator and having afrequency fixed to the center frequency of a frequency band assigned toan RF channel of BS digital broadcasting.

The frequency error generated when ODU down-converts the received radiowave appears in the BS-IF signal which is an intermediate signal andalso in the baseband signal.

By using the sine wave data sin θ₁ to sin θ₃ and cosine wave data cos θ₁to cos θ₃ received from the numerically controlled oscillators 1-1 to1-3, the complex calculation circuits 2-1 to 2-3 perform calculations ofthe formulas 2 to rotate the phase of the baseband signal:RIk=I×cos θ_(k) −Q×sin θ_(k)RQk=I×sin θ_(k) +Q×cos θ_(k)  (Formulas 2)where k is an integer of 0 to 3.

If the baseband signal received at the complex calculation circuit 2-1contains a frequency error of +1.3 MHz, the AFC circuit 11 performs acomplex number calculation of the phase signal θ₁ to set it to such avalue that the phase of the signal point assigned a predetermined signal(0 or 1) on the transmission side will not rotate.

If the baseband signal received at the complex calculation circuit 2-2does not contain a frequency error (a frequency error of 0 MHz), the AFCcircuit 11 performs a complex number calculation of the phase signal θ₂to set it to such a value that the phase of the signal point assigned apredetermined signal (0 or 1) on the transmission side will not rotate.

If the baseband signal received at the complex calculation circuit 2-3contains a frequency error of −1.3 MHz, the AFC circuit 11 performs acomplex number calculation of the phase signal θ₃ to set it to such avalue that the phase of the signal point assigned a predetermined signal(0 or 1) on the transmission side will not rotate on the reception side.

Namely, the AFC circuit 11 sets the phase signal θ₁ to such a value thatthe frame synchronization pattern 110 can be detected by receiving thebaseband signal which is contained in the intermediate frequency signal(BS-IF signal) in a predetermined frequency range higher than theoscillation frequency of a local oscillation signal generated by a localoscillator (not shown) and used for quasi-synchronization detection.

The AFC circuit 11 sets the phase signal θ₂ to such a value that theframe synchronization pattern 110 can be detected by receiving thebaseband signal which is contained in the intermediate frequency signal(BS-IF signal) in a predetermined frequency range including the samefrequency as the oscillation frequency of a local oscillator (notshown).

The AFC circuit 11 sets the phase signall θ₃ to such a value that theframe synchronization pattern 110 can be detected by receiving thebaseband signal which is contained in the intermediate frequency signal(BS-IF signal) in a predetermined frequency range lower than theoscillation frequency of a local oscillator (not shown).

Upon reception of the phase signals θ₁ to θ₃ from the AFC circuit 11,the numerically controlled oscillators 1-1 to 1-3 generate the sine wavedata sin θ₁ to sin θ₃ and cosine wave data cos θ₁ to cos θ₃ and supplythem to the complex calculation circuits 2-1 to 2-3.

The complex calculation circuits 2-1 to 2-3 input the obtained I signalsRI1 to RI3 and Q signals RQ1 to RQ3 to the band limit filters 3-1 to 3-3to limit the bands thereof and obtain the I signals DI1 to DI3 and Qsignals DQ1 to DQ3.

In this manner, the complex calculation circuits 2-1 to 2-3 can changethe frequency of the baseband signal so that the frame synchronizationpattern 110 can be detected in the range of ±2 MHz of the frequencyerror contained in the baseband signal. Therefore, if the frequencyerror generated when ODU down-converts is in the range of ±2 MHz, it ispossible to detect the frame synchronization pattern and acquire the RFchannel.

The I signals DI1 to DI3 and Q signals DQ1 to Dq3 output from the bandlimit filters 3-1 to 3-3 are input to the BPSK demappers 4-1 to 4-3 andto the selector 7.

The selector 7 selects a pair of the I signals DI1 to DI3 and Q signalsDQ1 to DQ3 output from one of the band limit filters 3-1 to 3-3, andsends the pair to the phase error detection circuit 8.

Whether the selector 7 selects which pair of the I signals DI1 to DI3and Q signals DQ1 to DQ3 is determined by the selection signal suppliedfrom the timing generator 6.

The operations up to outputting the selection signal from the timinggenerator 6 will be described.

When the I signals DI1 to DI3 and Q signals DQ1 to DQ3 output from theband limit filters 3-1 to 3-3 are input to the BPSK demappers 4-1 to4-3, the BPSK de-mapping circuits 20 to 27 recover the digital signals.

In this case, in order to convert the received signal point into thedigital signal, each of the BPSK de-mapping circuits 20 to 27 specifiesthe received signal point on the I-Q vector plane having the BPSKdecision criterion border line BL whose phase is rotated so as to matchthe I-Q vector plane rotated by φ=45°×n (n is an integer of 0 to 7).

The reason why the signal point is converted into the digital signal byusing the eight I-Q vector planes having the BPSK decision criterionborder lines BL whose phases are rotated, is as follows.

Namely, in the hierarchical transmission method of repetitivelytransmitting each frame by using a plurality of time division modulationmethods, the TMCC data 111 representative of the transmissionmultiplexing configuration identification data indicating themultiplexing configuration of modulation methods, is derived at thetiming generated by the frame synchronization pulse after the framesynchronization is established. By identifying the multiplexingconfiguration of the modulation method indicated by the TMCC data 111,the processes for each modulation method can be executed.

Since the 8PSK demodulation is also performed until the framesynchronization is established, the phase of the baseband signal mayrotate by φ=45°×n(n is an integer of 0 to 7) until the framesynchronization is demodulated, depending upon the phase of the carrierrecovered by the numerically controlled oscillators 1-1 to 1-3 and AFCcircuit 11.

For example, it is assumed that the bit “0” is assigned to the signalpoint position “0” shown in FIG. 2( c) and the bit “1” is assigned tothe signal point position “4”.

In this case, the signal points for the bits “0” and “1” specified bythe I signals DI1 to DI3 and Q signals DQ1 to DQ3 received at the BPSKdemappers 4-1 to 4-3 from the band limit filters 3-1 to 3-3, may appearat the signal point positions “0” and “4” at φ=0° shown in FIG. 2( c)which is same as those of the transmission side.

However, depending upon the phase of the carrier recovered by thenumerically controlled oscillators 1-1 to 1-3 and AFC circuit 11, thesignal points for the bits “0” and “1” may appear at the signal pointpositions “1” and “5” at the phase rotation of φ=45° shown in FIG. 2(a).

Alternatively, they may appear at the signal point positions “2” and “6”at the phase rotation of φ=90, or may appear at the signal pointpositions “0” and “4” at the phase rotation of φ=135°.

Since the phase may rotate by φ=45°×n (n is an integer of 0 to 7) untilthe frame synchronization pattern 110 is demodulated, it is necessary toreliably detect the frame synchronization pattern 110 even if it isdemodulated at each of eight phases.

From this reason, each of the BPSK demappers 4-1 to 4-3 has eight BPSGde-mapping circuit 20 to 27 and converts the signal point into a digitalsignal by using one of the eight I-Q vector planes having the BPSKdecision criterion border lines BL whose phases are rotated.

The bit streams (B0 to B7) of the digital signal recovered by the BPSKdemappers 4-1 to 4-3 are sent to the frame synchronization patterndetection circuits 5-1 to 5-3.

When the timing generator 6 is notified from one of the framesynchronization pattern detection circuits 5-1 to 5-3 that the framesynchronization pattern 110 was detected, it decides which one of theframe synchronization pattern detection circuits 5-1 to 5-3 detected theframe synchronization pattern 110, and sends the select signalcorresponding to the decision result.

Namely, if the timing generator 6 decides that the frame synchronizationpattern detection circuit 5-1 detected the frame synchronization pattern110, it sends the selection signal to the selector 7 to select the Isignal DI1 and Q signal DQ1 output from the band limit filter 3-1. Ifthe timing generator 6 decides that the frame synchronization patterndetection circuit 5-2 detected the frame synchronization pattern 110, itsends the selection signal to the selector 7 to select the I signal DI2and Q signal DQ2 output from the band limit filter 3-2. If the timinggenerator 6 decides that the frame synchronization pattern detectioncircuit 5-3 detected the frame synchronization pattern 110, it sends theselection signal to the selector 7 to select the I signal DI3 and Qsignal DQ3 output from the band limit filter 3-3.

In this manner, the timing generator 6 can send the selection signal formaking the selector 7 decide which pair of the I signals DI1 to DI3 andQ signals DQ1 to DQ3 is selected.

At the same time, the timing generator 6 establishes a framesynchronization at the timing when the timing generator receives anotice that the frame synchronization pattern 110 was detected, from oneof the frame synchronization pattern detection circuits 5-1 to 5-3.Then, the timing generator 6 generates a TMCC section signal forspecifying the TMCC section and sends it to the frequency errorcalculation circuit 9.

At the same time, the timing generator 6 sends a switch signal to theAFC circuit 11 to make it recover the carrier for acquiring an RFchannel. The switch signal corresponds to the decision result of whichone of the frame synchronization pattern detection circuits 5-1 to 5-3detected the frame synchronization pattern 110.

Namely, if the timing generator 6 decides that the frame synchronizationpattern detection circuit 5-1 detected the frame synchronization pattern110, it sends the switch signal to the AFC circuit 11, the switch signalinstructing the AFC circuit 11 to control the numerically controlledoscillator 1-1 by the phase signal θ₁ and recover the carrier. If thetiming generator 6 decides that the frame synchronization patterndetection circuit 5-2 detected the frame synchronization pattern 110, itsends the switch signal to the AFC circuit 11, the switch signalinstructing the AFC circuit 11 to control the numerically controlledoscillator 1-2 by the phase signal θ₂ and recover the carrier. If thetiming generator 6 decides that the frame synchronization patterndetection circuit 5-3 detected the frame synchronization pattern 110, itsends the switch signal to the AFC circuit 11, the switch signalinstructing the AFC circuit 11 to control the numerically controlledoscillator 1-3 by the phase signal θ₃ and recover the carrier.

The I signal DI and Q signal DQ selected by the selector 7 are sent tothe phase error detection circuit 8.

In accordance with the I signal DI and Q signal DQ received from theselector 7, the phase error detection circuit 8 specifies the signalpoint position on the I-Q vector plane, and calculates the phase error(reception point phase rotation angle) between the phase of the signalpoint position and the absolute phase.

The phase error detection circuit 8 sends a phase error signal PEDcorresponding to the calculated phase error to the frequency errorcalculation circuit 9 and loop filter 10.

The frequency error calculation circuit 9 specifies the TMCC sectionfrom the TMCC section signal received from the timing generator 6, andcalculates a difference (error frequency) Δf between the desiredfrequency and the frequency of the recovered carrier from the phaseerror in the TMCC section indicated by the phase error signal PEDreceived from the phase error detection circuit 8.

The frequency error calculation circuit 9 notifies the calculated errorfrequency Δf to the AFC circuit 11.

The loop filter 10 smoothes the phase error signal PED received from thephase error detection circuit 8 to obtain a phase adjustment signal LΔfwhich is sent to the AFC circuit 11.

The AFC circuit 11 adjusts one of the phase signals θ₁ to θ₃corresponding to the switch signal received from the timing generator 6,in accordance with the error frequency ΔF notified from the frequencyerror calculation circuit 9 and the phase adjustment signal LΔf receivedfrom the loop filter 10, and supplies the adjusted phase signal to acorresponding one of the numerically controlled oscillators 1-1 to 1-3.

In this manner, the sine wave data sin θ₁ to sin θ₃ and cosine wave datacos θ₁ to cos θ₃ for removing the frequency error of the carriercontained in the in-phase component I and quadrature component Q of thebaseband signal input to the complex calculation circuits 2-1 to 2-3 canbe generated and the channel having the desired frequency can beacquired.

As described above, in the synchronization acquiring circuit accordingto the first embodiment of the invention, the frame synchronizationpattern 110 contained in the baseband signal can be detected incorrespondence with the three frequency ranges representative ofdifferent frequency errors. Therefore, if the frequency error generatedwhen ODU down-converts a received radio wave is in a predetermined range(in a range of ±2 MHz), the frame synchronization pattern can bedetected quickly.

It is therefore possible to quickly establish a frame synchronizationand acquire an RF channel in a short time.

Second Embodiment

A synchronization acquiring circuit according to the second embodimentof the invention will be described.

FIG. 8 shows the structure of the synchronization acquiring circuitaccording to the second embodiment of the invention.

As shown in FIG. 8, the synchronization acquiring circuit has anumerically controlled oscillator 50, a complex calculation circuit 51,a band limit filter 52, a BPSK demapper 53, frame synchronizationpattern detection circuits 54-1 to 54-5, a timing generator 55, a phaseerror detection circuit 56, a frequency error calculation circuit 57, aloop filter 58, and an AFC circuit 59.

The numerically controlled oscillator 50 generates sine wave data sin θand cosine wave data cos θ respectively. The numerically controlledoscillator 50 generates a digital signal representative of the amplitudeof the sine wave data or cosine wave data corresponding to the phasesignal θ received from the AFC circuit 59, and sends it to the complexcalculation circuit 51.

The complex calculation circuit 51 is made of an inverter, a multiplierand the like, and performs calculations for removing the phase error andfrequency error of the quantized baseband signal.

More specifically, the complex calculation circuit 51 receives thein-phase component I and quadrature component Q of the baseband signalcontaining the phase error and frequency error. By using the sine wavedata sin θ and cosine wave data cos θ received from the numericallycontrolled oscillator 50, the complex calculation circuit 51 performs acalculation for rotating the phase of the baseband signal to therebygenerate an I (in-phase) signal RI and a Q (quadrature) signal RQ.

The complex calculation circuit 51 sends the generated I signal RI and Qsignal RQ to the band limit filter 52.

The band limit filter 52 is made of a digital roll-off filter or thelike having the raised cosine characteristics, and limits the pass bandof the I signal RI and Q signal RQ received from the complex calculationcircuit 51 to thereby generate a data waveform having no inter-codeinterference. The band limit filter 52 sends the band-limited I signalDI and Q signal DQ of the I signal RI and Q signal RQ received from thecomplex calculation circuit 51, to the BPSK demapper 53.

The band limit filter 52 also sends the band-limited I signal DI and Qsignal DQ to the phase error detection circuit 56.

The BPSK demapper 53 recovers the digital signal from the signal pointposition of the baseband signal in the manner opposite to the BPSKmapping on the transmission side, in order to detect the framesynchronization pattern 110 of 20 symbols transmitted through BPSKmodulation.

The BPSK demapper 53 has eight BPSK de-mapping circuits 20 to 27 similarto the synchronization acquiring circuit of the first embodiment.

The BPSK de-mapping circuits 20 to 27 send bit streams B0 to B7 of therecovered digital signals to the frame synchronization pattern detectioncircuits 54-1 to 54-5.

The frame synchronization pattern detection circuits 54-1 to 54-5 detectframe synchronization patterns from the bit streams B0 to B7 output fromthe BPSK de-mapping circuits 20 to 27 of the BPSK demapper 53.

Each of the frame synchronization pattern detection circuits 54-1 to54-5 detects the frame synchronization pattern 110 in the frequencyrange corresponding to the frequency error contained in the basebandsignal.

For example, the frame synchronization pattern detection circuit 54-1detects the frame synchronization pattern 110 if the frequency error ofthe baseband signal is in the range from +2.1 MHz to +1.4 MHz.

Similarly the frame synchronization pattern detection circuits 54-2,54-3, 54-4, and 54-5 detect the frame synchronization pattern 110 if thefrequency error is in the ranges from +1.4 MHz to +700 kHz, from +700kHz to −700 kHz, from −700 kHz to −1.4 MHz, and from −1.4 MHz to −2.1MHz.

The frame synchronization pattern detection circuit 54-1 has eightsynchronization detection circuits 40-1 to 47-1 and an OR gate 48-1 asshown in FIG. 9, in order to detect the frame synchronization pattern110 if the baseband signal received at the complex calculation circuit51 has a frequency error in the range from +2.1 MHz to +1.4 MHz.

In order to detect the frame synchronization pattern 110 correctly inthe case that the frequency error of the baseband signal is in the rangefrom +2.1 MHz to +1.4 MHz, for example, as shown in FIGS. 10( a) to10(e), a BPSK decision criterion border line LN on the I-Q vector planeis rotated four times along the same phase direction while 20 symbols ofthe frame synchronization pattern are received.

The signal point positions shown in FIGS. 10( a) to 10(e) are assignedto the bit “1” on the transmission side.

The synchronization detection circuits 40-1 to 47-1 of the framesynchronization pattern detection circuit 54-1 detect the framesynchronization pattern 110 by using four of the eight bit streams B0 toB7 received from the eight BPSK de-mapping circuits 20 to 27 of the BPSKdemapper 53.

Consider for example the case wherein the synchronization detectioncircuit 40-1 is used as the circuit for detecting the framesynchronization pattern 110 from the digital signals converted by usingthe I-Q vector plane whose BPSK decision criterion border line LN isrotated in the order shown in FIGS. 10( a) to 10(e).

In this case, as shown in FIG. 11, the synchronization detection circuit40-1 has six AND gates A10-1 to A15-1, and delay latches D₀ to D₁₉serially connected for respective bit streams.

By using the delay latches D₀ to D₁₉, this synchronization detectioncircuit 40-1 delays the bit stream B2 received from the BPSK de-mappingcircuit 22 which demaps by using the I-Q vector plane shown in FIG. 4(c). The AND gate A10-1 outputs a high level voltage when the state(D₃D₂D₁D₀) of the delay latches D₀ to D₃) is (1000). The AND gate A11-1outputs a high level voltage when the state (D₁₉D₁₈D₁₇D₁₆) of the delaylatches D₁₆ to D₁₉ is (1110).

By using the delay latches D₀ to D₁₅, the synchronization detectioncircuit 40-1 delays the bit stream B4 received from the BPSK de-mappingcircuit 24 which demaps by using the I-Q vector plane shown in FIG. 4(e). The AND gate A12-1 outputs a high level voltage when the state(D₁₅D₁₄D₁₃D₁₂) of the delay latches D₁₂ to D₁₅) is (1100).

By using the delay latches D₀ to D₁₁, the synchronization detectioncircuit 40-1 delays the bit stream B6 received from the BPSK de-mappingcircuit 26 which demaps by using the I-Q vector plane shown in FIG. 4(g). The AND gate A13-1 outputs a high level voltage when the state(D₁₁D₁₀D₉D₈) of the delay latches D₈ to D₁₁) is (1101).

By using the delay latches D₀ to D₇, the synchronization detectioncircuit 40-1 delays the bit stream B0 received from the BPSK de-mappingcircuit 20 which demaps by using the I-Q vector plane shown in FIG. 4(a). The AND gate A14-1 outputs a high level voltage when the state(D₇D₆D₅D₄) of the delay latches D₄ to D₇) is (0010).

The AND gate A15-1 outputs a high level voltage when all the AND gatesA10-1 to A14-1 output the high level voltage. Therefore, thesynchronization detection circuit 40-1 notifies the timing generator 55of a detection of a frame synchronization pattern 110 via the OR gate48-1.

Similar to the synchronization detection circuit 40-1, thesynchronization detection circuits 41-1 to 47-1 shown in FIG. 9 detectthe frame synchronization pattern 110 by using four of the bit streamsB0 to B7 received from the eight BPSK de-mapping circuits 20 to 27 ofthe BPSK demapper 53.

The synchronization detection circuits 40-1 to 47-1 are structured sothat they can deal with different reception point phase rotation anglesby 45°×n (n is an integer of 0 to 7) at the time when the first bits ofthe frame synchronization pattern 110 are received.

The synchronization detection circuits 40-1 to 47-1 may share the delaylatches D₀ to D₁₉ for delaying each of the bit streams B0 to B7. In thiscase, the connection wiring is formed in accordance with the state ofthe delay latches D₀ to D₁₉ for obtaining the logical products.

The frame synchronization pattern detection circuit 54-2 shown in FIG. 8has eight synchronization detection circuits 40-2 to 47-2 and an OR gate48-2 as shown in FIG. 12, in order to detect the frame synchronizationpattern 110 if the baseband signal received at the complex calculationcircuit 51 has a frequency error in the range from +1.4 MHz to +700 kHz.

In order to detect the frame synchronization pattern 110 correctly inthe case that the frequency error of the baseband signal is in the rangefrom +1.4 MHz to +700 kHz, for example, as shown in FIGS. 13( a) to13(c), the BPSK decision criterion border line LN on the I-Q vectorplane is rotated twice along the same phase direction while 20 symbolsof the frame synchronization pattern are received.

The signal point positions shown in FIGS. 13( a) to 13(c) are assignedto the bit “1” on the transmission side.

The synchronization detection circuits 40-2 to 47-2 of the framesynchronization pattern detection circuit 54-2 detect the framesynchronization pattern 110 by using three of the eight bit streams B0to B7 received from the eight BPSK de-mapping circuits 20 to 27 of theBPSK demapper 53.

Consider for example the case wherein the synchronization detectioncircuit 40-2 is used as the circuit for detecting the framesynchronization pattern 110 from the digital signals converted by usingthe I-Q vector plane whose BPSK decision criterion border line LN isrotated in the order shown in FIGS. 13( a) to 13(c).

In this case, as shown in FIG. 14, the synchronization detection circuit40-2 has four gates A10-2 to A13-2, and delay latches D₀ to D₁₉ seriallyconnected for respective bit streams.

By using the delay latches D₀ to D₁₉ this synchronization detectioncircuit 40-2 delays the bit stream B2 received from the BPSK de-mappingcircuit 22 which demaps by using the I-Q vector plane shown in FIG. 4(c). The AND gate A10-2 outputs a high level voltage when the state(D₁₉D₁₈D₁₇D₁₆D₁₅D₁₄D₁₃) of the delay latches D₁₃ to D₁₉) is (1110110).

By using the delay latches D₀ to D₁₂, the synchronization detectioncircuit 40-2 delays the bit stream B4 received from the BPSK de-mappingcircuit 24 which demaps by using the I-Q vector plane shown in FIG. 4(e). The AND gate A11-2 outputs a high level voltage when the state(D₁₂D₁₁D₁₀D₉D₈D₇) of the delay latches D₇ to D₁₂) is (011010).

By using the delay latches D₀ to D₆, the synchronization detectioncircuit 40-2 delays the bit stream B6 received from the BPSK de-mappingcircuit 26 which demaps by using the I-Q vector plane shown in FIG. 4(g). The AND gate A12-2 outputs a high level voltage when the state(D₆D₅D₄D₃D₂D₁D₀) of the delay latches D₀ to D₆) is (0101000).

The AND gate A13-2 outputs a high level voltage when all the AND gatesA10-2 to A12-2 output the high level voltage. Therefore, thesynchronization detection circuit 40-2 notifies the timing generator 55of a detection of a frame synchronization pattern 110 via the OR gate48-2.

Similar to the synchronization detection circuit 40-2, thesynchronization detection circuits 41-2 to 47-2 shown in FIG. 12 detectthe frame synchronization pattern 110 by using three of the bit streamsB0 to B7 received from the eight BPSK de-mapping circuits 20 to 27 ofthe BPSK demapper 53.

The synchronization detection circuits 40-2 to 47-2 are structured sothat they can deal with different reception point phase rotation anglesby 45°×n (n is an integer of 0 to 7) at the time when the first bits ofthe frame synchronization pattern 110 are received.

The synchronization detection circuits 40-2 to 47-2 may share the delaylatches D₀ to D₁₉ for delaying each of the bit streams B0 to B7. In thiscase, the connection wiring is formed in accordance with the states ofthe delay latches D₀ to D₁₉ for obtaining the logical products.

The frame synchronization pattern detection circuit 54-3 shown in FIG. 8detects the frame synchronization pattern 110 if the baseband signalreceived at the complex calculation circuit 51 has a frequency error inthe range from +700 kHz to −700 kHz, and has the same structure as thatof the frame synchronization pattern detection circuits 5-1 to 5-3 ofthe first embodiment.

The frame synchronization pattern detection circuit 54-4 detects theframe synchronization pattern 110 if the baseband signal received at thecomplex calculation circuit 51 has a frequency error in the range from−700 kHz to −1.4 MHz. This frame synchronization pattern detectioncircuit 54-4 is structured in order to recover the digital signal byrotating the BPSK decision criterion border line LN twice in the phasedirection opposite to that of the frame synchronization detectioncircuit 54-2 while the symbols of the frame synchronization pattern 13are received.

The frame synchronization pattern detection circuit 54-5 detects theframe synchronization pattern 110 if the baseband signal received at thecomplex calculation circuit 51 has a frequency error in the range from−1.4 MHz to −2.1 MHz. This frame synchronization pattern detectioncircuit 54-5 is structured in order to recover the digital signal byrotating the BPSK decision criterion border line LN four times in thephase direction opposite to that of the frame synchronization detectioncircuit 54-2 while the symbols of the frame synchronization pattern 13are received.

The timing generator 55 establishes a frame synchronization when it isnotified from the frame synchronization pattern detection circuits 54-1to 54-5 that the frame synchronization pattern 110 was detected.

After the timing generator 55 establishes the frame synchronization, itderives the TMCC data 111 to identify the frame multiplex configuration,and sends a TMCC section signal to the frequency error calculationcircuit 57 to specify the TMCC section.

When the timing generator 55 receives a notice of a detection of theframe synchronization pattern 110 from one of the frame synchronizationpattern detection circuits 54-1 to 54-5, it decides which one of theframe synchronization pattern detection circuits 54-1 to 54-5 detectedthe frame synchronization pattern. In accordance with this decisionresult, the timing generator 55 notifies the AFC circuit 59 of anoff-set frequency for acquiring an RF channel.

In accordance with the I signal DI and W signal DQ received from theband limit filter 52, the phase error detection circuit 56 specifies thesignal point position on the I-Q vector plane to obtain a phase error(received signal phase rotation angle) between the phase of the signalpoint position and the absolute phase.

The phase error detection circuit 56 generates a phase error signal PEDcorresponding to the obtained phase error, and sends it to the frequencyerror calculation circuit 57 and loop filter 58.

The frequency error calculation circuit 57 specifies the TMCC sectionfrom the TMCC section signal received from the timing generator 55, andcalculates a difference (error frequency) Δf between a desired frequencyand the frequency of the recovered carrier, in accordance with the phaseerror in the TMCC section represented by the phase error signal PEDreceived from the phase error detection circuit 56.

The frequency error calculation circuit 57 notifies the calculated errorfrequency Δf to the AFC circuit 59.

The loop filter 58 is a low pass filter for smoothing the phase errorsignal PED received from the phase error detection circuit 56, andsupplies the smoothed phase error signal PED to the AFC circuit 59 as aphase adjustment signal LΔf.

The AFC circuit 59 is used for generating a phase signal 0 correspondingto the error frequency Δf supplied from the frequency error calculationcircuit 57 and the phase adjustment signal LΔf supplied from the loopfilter 58, so as to recover the carrier.

The AFC circuit 59 controls the numerically controlled oscillator 50 bythe phase signal corresponding to the off-set frequency notified fromthe timing generator 55, to thereby make the numerically controlledoscillator 50 generate the sine wave data sin and cosine wave data coswhich allow the frame synchronization pattern detection circuit 54-3 todetect the frame synchronization patten 110.

Next, the operation of the synchronization acquiring circuit accordingto the second embodiment of the invention will be described.

In the synchronization acquiring circuit of the second embodiment of theinvention, the numerically controlled oscillator 50, complex calculationcircuit 51, band limit filter 52, phase error detection circuit 56,frequency error calculation circuit 57, loop filter 58 and AFC circuit59 constitute a carrier reproduction loop which removes the frequencyerror of the carrier contained in the in-phase component I andquadrature component Q of the baseband signal input to the complexcalculation circuit 51.

The numerically controlled oscillator 50, complex calculation circuit 51and band limit filter 52 operate in the manner similar to thenumerically controlled oscillators 1-1 to 1-3, complex calculationcircuits 2-1 to 2-3 and band limit filters 3-1 to 3-3 of thesynchronization acquiring circuit of the first embodiment.

If the baseband signal received at the complex calculation circuit 51contains no frequency error (frequency error of 0 Hz), the AFC circuit59 performs a complex number calculation of the phase signal to set itto such a value that the phase of the signal point assigned apredetermined signal (0 or 1) on the transmission side will not rotateon the reception side.

The I signal DI and Q signal DQ output from the band limit filter 52 areinput to the BPSK demapper 53 and phase error detection circuit 56.

The BPSK de-mapping circuits 20 to 27 of the BPSK demapper 53 recoverdigital signals and send them to the frame synchronization patterndetection circuits 54-1 to 54-5.

The frame synchronization pattern detection circuits 54-1 to 54-5 detectthe frame synchronization pattern 110 in the different ranges of afrequency error of the baseband signal.

Namely, the frame synchronization detection circuit 54-1 detects theframe synchronization pattern 110 if the frequency error of the basebandreceived at the complex calculation circuit 51 is in the range from +2.1MHz to +1.4 MHz.

Similarly, the frame synchronization detection circuits 54-2 to 54-5detect the frame synchronization pattern 110, respectively in thefrequency error ranges from +1.4 MHz to +700 kHz, from +700 kHz to −700kHz, from −700 kHz to −1.4 MHz, and from −1.4 MHz to −2.1 MHz.

The frame synchronization pattern detection circuit 54-3 can detect theframe synchronization pattern 110, if the center frequency in thefrequency band assigned to an RF channel is down-converted by ODU (notshown) so as to correspond to the frequency of the intermediatefrequency signal (BS-IF signal) in the predetermined frequency rangeincluding the oscillation frequency of the local oscillator (not shown).

The frame synchronization pattern detection circuit 54-2 can detect theframe synchronization pattern 110, if the center frequency in thefrequency band assigned to an RF channel is down-converted by ODU (notshown) so as to correspond to the frequency of the intermediatefrequency signal (BS-IF signal) in the predetermined frequency rangehigher than the frequency range in which the frame synchronizationpattern detection circuit 54-3 can detect the frame synchronizationpattern 110.

The frame synchronization pattern detection circuit 54-1 can detect theframe synchronization pattern 110, if the center frequency in thefrequency band assigned to an RF channel is down-converted by ODU (notshown) so as to correspond to the frequency of the intermediatefrequency signal (BS-IF signal) in the predetermined frequency rangehigher than the frequency range in which the frame synchronizationpattern detection circuit 54-2 can detect the frame synchronizationpattern 110.

The frame synchronization pattern detection circuit 54-4 can detect theframe synchronization pattern 110, if the center frequency in thefrequency band assigned to an RF channel is down-converted by ODU (notshown) so as to correspond to the frequency of the intermediatefrequency signal (BS-IF signal) in the predetermined frequency rangelower than the frequency range in which the frame synchronizationpattern detection circuit 54-3 can detect the frame synchronizationpattern 110.

The frame synchronization pattern detection circuit 54-5 can detect theframe synchronization pattern 110, if the center frequency in thefrequency band assigned to an RF channel is down-converted by ODU (notshown) so as to correspond to the frequency of the intermediatefrequency signal (BS-IF signal) in the predetermined frequency rangelower than the frequency range in which the frame synchronizationpattern detection circuit 54-4 can detect the frame synchronizationpattern 110.

When the frame synchronization detection circuits 54-1 to 54-5 detectthe frame synchronization pattern 110, it notifies this effect to thetiming generator 55.

When the timing generator 55 is notified from one of the framesynchronization pattern detection circuits 54-1 to 54-5 that the framesynchronization pattern 110 was detected, in response to this notice,the timing generator 55 establishes the frame synchronization, generatesa TMCC section signal for specifying the TMCC section, and sends it tothe frequency error calculation circuit 57.

In this case, the timing generator 55 decides which one of the framesynchronization pattern detection circuits 54-1 to 54-5 detected theframe synchronization pattern 110, and in accordance with this decisionresult, the timing generator 55 notifies the AFC circuit 59 of theoff-set frequency for acquiring the RF channel.

More specifically, if the timing generator 55 decides that the framesynchronization pattern detection circuit 54-1 detected the framesynchronization pattern 110, the timing generator 55 notifies the AFCcircuit 59 of the off-set frequency of +1.75 MHz.

If the timing generator 55 decides that the frame synchronizationpattern detection circuit 54-2 detected the frame synchronizationpattern 110, the timing generator 55 notifies the AFC circuit 59 of theoff-set frequency of +1.05 MHz.

If the timing generator 55 decides that the frame synchronizationpattern detection circuit 54-3 detected the frame synchronizationpattern 110, the timing generator 55 notifies the AFC circuit 59 of theoff-set frequency of 0 MHz.

If the timing generator 55 decides that the frame synchronizationpattern detection circuit 544 detected the frame synchronization pattern110, the timing generator 55 notifies the AFC circuit 59 of the off-setfrequency of −1.05 MHz.

If the timing generator 55 decides that the frame synchronizationpattern detection circuit 54-5 detected the frame synchronizationpattern 110, the timing generator 55 notifies the AFC circuit 59 of theoff-set frequency of −1.75 MHz.

The AFC circuit 59 controls the numerically controlled oscillator 50 bythe phase signal corresponding to the off-set frequency notified fromthe timing generator 55 to generate the sine wave data sin and cosinedata cos.

By using the sine wave data sin and cosine data cos defined by the phasesignal corresponding to the off-set frequency, the complex calculationcircuit 51 removes the frequency error contained in the in-phasecomponent I and quadrature component Q of the baseband signal.

In this manner, if the frequency error of an RF channel to be acquiredis outside the range of ±700 kHz, the frequency error is inside therange of ±35 kHz.

Therefore, when one of the frame synchronization pattern detectioncircuits 54-1 to 54-5 detects the frame synchronization pattern 110, thecomplex calculation circuit 51 changes the frequency of the basebandsignal so that the frame synchronization pattern detection circuit 54-3can detect the frame synchronization pattern.

Since the band to be covered by the frame synchronization patterndetection circuit 54-3 is as broad as 1.4 4 MHz, the RF channel can bestably acquired.

Thereafter, in accordance with the I signal DI and Q signal DQ receivedfrom the band limit filter 52, the phase error detection circuit 56specifies the signal point position on the I-Q vector plane and obtainsthe phase error (received signal phase rotation angle) between the phaseof the signal point position and the absolute phase.

The phase error detection circuit 56 generates the phase error signalPED corresponding to the obtained phase error, and sends it to thefrequency error calculation circuit 57 and loop filter 58.

The frequency error calculation circuit 57 specifies the TMCC sectionfrom the TMCC section signal received from the timing generator 55, andcalculates a difference (error frequency) Δf between the desiredfrequency and the frequency of the recovered carrier by using the phaseerror in the TMCC section indicated by the phase error signal PEDreceived from the phase error detection circuit 56.

The frequency error calculation circuit 57 notifies the calculated errorfrequency Δf to the AFC circuit 59.

The loop filter 58 smoothes the phase error signal PED received from thephase error detection circuit 56 to obtain a phase adjustment signal LΔfwhich is sent to the AFC circuit 59.

The AFC circuit 59 adjusts the phase signal in accordance with the errorfrequency ΔF notified from the frequency error calculation circuit 57and the phase adjustment signal LΔf received from the loop filter 58 tocontrol the numerically controlled oscillator 50 and recover thecarrier.

In this manner, the sine wave data sin and cosine wave data cos forremoving the frequency error of the carrier contained in the in-phasecomponent I and quadrature component Q of the baseband signal input tothe complex calculation circuit 51 can be generated and the channelhaving the desired frequency can be acquired.

As described above, in the synchronization acquiring circuit accordingto the second embodiment of the invention, the frame synchronizationpattern detection circuits 54-1 to 54-5 are provided for detecting theframe synchronization pattern 110 in correspondence with the fivefrequency ranges representative of different frequency errors containedin the baseband signal. Therefore, even if the baseband signal has alarge frequency error, the frame synchronization pattern can be detectedinstantly. If the frequency error generated when ODU down-converts is inthe predetermined range (in the range of ±2 MHz), the framesynchronization pattern 110 can be detected at once.

When one of the frame synchronization pattern detection circuits 54-1 to54-5 detects the frame synchronization pattern 110, the off-setfrequency is set so that the frame synchronization pattern detectioncircuit 54-3 capable of detecting the frame synchronization pattern inthe broadest range of the frequency error, can establish the framesynchronization.

It is therefore possible to quickly establish a frame synchronizationand acquire an RF channel in a short time and stably.

The present invention is not limited only to receiving BS digitalbroadcasting, but is applicable to any receiver which receives thebaseband signal containing a frequency error and establishes a framesynchronization.

INDUSTRIAL APPLICABILITY

As described so far, according to the present invention, the framesynchronization pattern is detected in correspondence with the frequencyranges representative of different frequency errors contained in thebaseband signal, so that the frame synchronization can be establishedquickly and an RF channel can be acquired in a short time.

1. A synchronization acquiring circuit for receiving a baseband signaltransferred as an intermediate frequency signal obtained bydown-converting a received radio wave and for acquiring a radiofrequency channel, comprising: a plurality of pattern detection meansdisposed in parallel each performing an operation of receiving thebaseband signal transferred by the intermediate frequency signal in adifferent frequency range and detecting a predetermined framesynchronization pattern; and carrier recovery means for establishing aframe synchronization and recovering a carrier to be used for removing afrequency error of the baseband signal when one of said plurality ofpattern detection means detects the frame synchronization pattern.
 2. Asynchronization acquiring circuit for receiving a baseband signaltransferred as an intermediate frequency signal obtained bydown-converting a received radio wave and for acquiring a radiofrequency channel, comprising: first pattern detection means forreceiving the baseband signal transferred by the intermediate frequencysignal in a predetermined frequency range and detecting a predeterminedframe synchronization pattern; second pattern detection means forreceiving baseband signal transferred by the intermediate frequencysignal in a frequency range higher than the frequency range of theintermediate frequency signal transferring the baseband signal fromwhich said first pattern detection means can detect the framesynchronization pattern, and detecting the predetermined framesynchronization pattern; third pattern detection means for receiving thebaseband signal transferred by the intermediate frequency signal in afrequency range lower than the frequency range of the intermediatefrequency signal transferring the baseband signal from which said firstpattern detection means can detect the frame synchronization pattern,and detecting the predetermined frame synchronization pattern; andcarrier recovery means for establishing a frame synchronization andrecovering a carrier to be used for removing a frequency error of thebaseband signal when one of said first to third pattern detection meansdetects the frame synchronization pattern.
 3. A synchronizationacquiring circuit according to claim 2, wherein each of said first tothird pattern detection means comprises: signal conversion means forspecifying a phase of the received baseband signal and converting thephase into a digital signal corresponding to the specified phase; andsignal decision means for deciding whether the digital signal generatedthrough conversion by said signal conversion means contains thepredetermined frame synchronization pattern.
 4. A synchronizationacquiring circuit according to claim 3, wherein: said signal conversionmeans has: eight de-mapping means each for specifying the phase of thebaseband signal on a phase plane having a decision criterion border linewhose phase is rotated by =45°×n (where n is an integer of 0 to 7) andobtaining the converted digital signal, the decision criterion borderline being used for specifying a value of the converted digital signalcorresponding to the specified phase of the baseband signal; and saidsignal decision means has: eight sequence decision means for decidingwhether each digital signal sequence generated through conversion byeach of said eight de-mapping means contains the predetermined framesynchronization pattern; and means for notifying said carrier recoverymeans of that the frame synchronization pattern was detected, if atleast one of said eight sequence decision means decides that the digitalsignal sequence contains the predetermined frame synchronizationpattern.
 5. A synchronization acquiring circuit according to any one ofclaims 2, 3 and 4, wherein: each of said first to third patterndetection means comprises: waveform data making means for creatingwaveform data to be used for rotating a phase of the baseband signal;and complex calculation means for rotating the phase of the basebandsignal by executing a complex number calculation between the waveformdata created by said waveform making means and the received basebandsignal; and said carrier recovery means comprises: identification meansfor identifying one of said first to third pattern detection means whichdetected the frame synchronization pattern; signal selection means forselecting the baseband signal whose phase was rotated by said complexcalculation means of one of said first to third pattern detection meansidentified by said identification means; phase error identificationmeans for identifying a phase error by comparing the phase of thebaseband signal selected by said signal selection means and an absolutephase; frequency error identification means for identifying a frequencyerror contained in the baseband signal in accordance with the phaseerror identified by said phase error identification means; and carrierrecovery means for recovering a carrier to be used for removing thephase error and frequency error contained in the baseband signal, bycontrolling said waveform data making means of one of said first tothird pattern detection means identified by said identification means inaccordance with the phase error identified by said phase erroridentification means and the frequency error identified by saidfrequency error identification means.
 6. A synchronization acquiringcircuit for receiving a baseband signal transferred as an intermediatefrequency signal obtained through frequency conversion of a receivedradio wave and for acquiring a radio frequency channel of BS digitalbroadcasting, the circuit comprising: a plurality of framesynchronization pattern detecting means (e.g., 54-1˜54-5) for receivingthe baseband signal which contains a frequency error corresponding to awhole frequency range of the intermediate frequency signal, to detect aframe synchronization pattern through conversion into a digital signaland in correspondence with the frequency error, wherein different onesof the plurality of synchronization pattern detecting means correspondto different ranges of frequency error, respectively; and wherein acarrier synchronized with a frequency of the baseband signal isrecovered on the basis of a range of frequency error contained in thebaseband signal from which the frame synchronization pattern wasdetected by any of the plurality of detecting means, to thereafterestablish a frame synchronization.
 7. A synchronization acquiringcircuit for receiving a baseband signal transferred as an intermediatefrequency signal obtained by down-converting a received radio wave andfor acquiring a radio frequency channel, comprising: signal conversionmeans for identifying a phase of a received baseband signalphase-modulated in a symbol unit and converting the baseband signal intoa digital signal corresponding to the identified phase; a plurality ofpattern detection means disposed in parallel for detecting apredetermined frame synchronization pattern transferred by the basebandsignal, in accordance with the digital signal generated throughconversion by said signal conversion means, each of said plurality ofpattern detection means being related to a frequency of the intermediatefrequency signal in a different frequency range; and frequency controlmeans for changing the frequency of the baseband signal by using anoff-set frequency corresponding to a frequency error contained in thebaseband signal, when one of said plurality of pattern detection meansdetects the frame synchronization pattern, and for establishing a framesynchronization after said signal conversion means identifies the phaseof the baseband signal.
 8. A synchronization acquiring circuit forreceiving a baseband signal transferred as an intermediate frequencysignal obtained by down-converting a received radio wave and foracquiring a radio frequency channel, comprising: first pattern detectionmeans for detecting a predetermined frame synchronization patterntransferred by the baseband signal, in accordance with the digitalsignal generated through conversion by said signal conversion means, ifa center frequency of a range assigned to the radio frequency channelcorresponds to a frequency of the intermediate frequency signal in apredetermined frequency range; second pattern detection means fordetecting the predetermined frame synchronization pattern transferred bythe baseband signal, in accordance with the digital signal generatedthrough conversion by said signal conversion means, if the centerfrequency of the range assigned to the radio frequency channelcorresponds to the frequency of the intermediate frequency signal in afrequency range higher than the frequency range of the intermediatefrequency signal from which said first pattern detection means candetect the frame synchronization pattern; third pattern detection meansfor detecting the predetermined frame synchronization patterntransferred by the baseband signal, in accordance with the digitalsignal generated through conversion by said signal conversion means, ifthe center frequency of the range assigned to the radio frequencychannel corresponds to the frequency of the intermediate frequencysignal in a frequency range higher than the frequency range of theintermediate frequency signal from which said second pattern detectionmeans can detect the frame synchronization pattern; fourth patterndetection means for detecting the predetermined frame synchronizationpattern transferred by the baseband signal, in accordance with thedigital signal generated through conversion by said signal conversionmeans, if the center frequency of the range assigned to the radiofrequency channel corresponds to the frequency of the intermediatefrequency signal in a frequency range lower than the frequency range ofthe intermediate frequency signal from which said first patterndetection means can detect the frame synchronization pattern; fifthpattern detection means for detecting the predetermined framesynchronization pattern transferred by the baseband signal, inaccordance with the digital signal generated through conversion by saidsignal conversion means, if the center frequency of the range assignedto the radio frequency channel corresponds to the frequency of theintermediate frequency signal in a frequency range lower than thefrequency range of the intermediate frequency signal from which saidfirst to fourth detection means can detect the frame synchronizationpattern; and frequency control means for transforming the frequency ofthe baseband signal by using an off-set frequency corresponding to afrequency error contained in the baseband signal, when one of said firstto fifth pattern detection means detects the frame synchronizationpattern, for making said signal conversion means identify a phase of thebaseband signal, and for making said first pattern detection meansdetect the frame synchronization pattern to thereafter establish a framesynchronization.
 9. A synchronization acquiring circuit according toclaim 8, wherein: said signal conversion means has: eight de-mappingmeans each for specifying the phase of the baseband signal on a phaseplane having a decision criterion border line whose phase is rotated by=45°×n (where n is an integer of 0 to 7) and obtaining the converteddigital signal, the decision criterion border line being used forspecifying a value of the converted digital signal corresponding to thespecified phase of the baseband signal; said first pattern detectionmeans has: eight sequence decision means each for deciding whether eachdigital signal sequence generated through conversion by each of saideight de-mapping means contains the predetermined frame synchronizationpattern; and means for notifying said frequency control means of thatthe frame synchronization pattern was detected, if at least one of saideight sequence decision means decides that the frame synchronizationpattern is contained; said second and fourth pattern detection meanshave each: eight first rotation sequence decision means for decidingwhether the predetermined frame synchronization pattern is contained, byusing three of eight digital sequences generated through conversion bysaid eight de-mapping means; and said third and fifth pattern detectionmeans have each: eight second rotation sequence decision means fordeciding whether the predetermined frame synchronization pattern iscontained, by using four of eight digital sequences generated throughconversion by said eight de-mapping means.
 10. A synchronizationacquiring circuit according to claim 9, wherein said first and secondrotation sequence decision means each have: delay means for delayingeach bit of the digital signal sequence; and means for deciding whetherthe predetermined frame synchronization pattern is contained, byderiving the digital signal sequence from said delay means in a mannerthat the phase of the decision criterion border line rotates in the samedirection as a signal reception time lapses.
 11. A synchronizationacquiring circuit according to claim 10, wherein: said first rotationsequence decision means of said second pattern detection means and saidfirst rotation sequence decision means of said fourth pattern detectionmeans derive the digital signal sequence from said delay means in amanner that the phase of the decision criterion border lines rotate inopposite directions as a signal reception time lapses; and said secondrotation sequence decision means of said third pattern detection meansand said second rotation sequence decision means of said fifth patterndetection means derive the digital signal sequence from said delay meansin a manner that the phase of the decision criterion border lines rotatein opposite directions as a signal reception time lapses.
 12. Asynchronization acquiring circuit according to any one of claims 7 to11, wherein said frequency control means comprises: waveform data makingmeans for creating waveform data to be used for rotating a phase of thebaseband signal; complex calculation means for rotating the phase of thebaseband signal by executing a complex number calculation between thewaveform data created by said waveform making means and the receivedbaseband signal; phase error identification means for identifying aphase error by comparing the phase of the baseband signal rotated bysaid complex calculation means and an absolute phase; frequency erroridentification means for identifying a frequency error contained in thebaseband signal in accordance with the phase error identified by saidphase error identification means; and carrier recovery means forrecovering a carrier to be used for removing the phase error andfrequency error contained in the baseband signal, by controlling saidwaveform data making means in accordance with the phase error identifiedby said phase error identification means and the frequency erroridentified by said frequency error identification means.
 13. Asynchronization acquiring method of receiving a baseband signaltransferred as an intermediate frequency signal obtained bydown-converting a received radio wave and for acquiring a radiofrequency channel, comprising: a first pattern detection step ofreceiving the baseband signal transferred by the intermediate frequencysignal in a predetermined frequency range and detecting a predeterminedframe synchronization pattern; a second pattern detection step ofreceiving, at the same time as said first pattern detection step, thebaseband signal transferred by the intermediate frequency signal in afrequency range higher than the frequency range of the intermediatefrequency signal transferring the baseband signal from which said firstpattern detection step can detect the frame synchronization pattern, anddetecting the predetermined frame synchronization pattern; a thirddetection step of receiving, at the same time as said first and secondpattern detection steps, the baseband signal transferred by theintermediate frequency signal in a frequency range lower than thefrequency range of the intermediate frequency signal transferring thebaseband signal from which said first pattern detection step can detectthe frame synchronization pattern, and detecting the predetermined framesynchronization pattern; and a carrier recovery step of establishing aframe synchronization and recovering a carrier to be used for removing afrequency error of the baseband signal when one of said first to thirdpattern detection steps detects the frame synchronization pattern.